Development of optimal method of hardware implementation of the SM4 and SM4_Mix encryption algorithms

Abstract

SM4 is extensively utilized in WLAN WAPI resource-constrained devices. This study introduces an 8-bit iteration structure for SM4 at an ultra-low cost, where key expansion and encryption alternate with only one S-Box. Additionally, to reduce area usage, an on-the-fly key expansion mechanism is employed to reserve memory for round keys, and constants keys are dynamically generated by an equation rather than being read from a large look-up table. The ASIC hardware implementation results indicate that our design has a gate count of only 2.47 K, achieving an approximately 16.0% reduction in area compared to recent works.